1. Field of the Invention
The present invention relates to memories for computers and other electronic devices, and more particularly, to flash memories and circuits that control the threshold voltage distribution of the flash memories after erase.
2. Description of Related Art
Flash EPROMs (erasable programmable read only memories) are a growing class of non-volatile storage integrated circuits. These flash EPROMs have the capability of electrically erasing, programming or reading a memory cell in the chip. The entire array can be simultaneously erased electrically. The flash EPROM can also be randomly read or written.
The cells themselves use only a single device per cell and are formed using so-called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically made of polysilicon, which are insulated from the channel of the transistor by a thin layer of oxide or other insulating material, and insulated from the control gate word line of the transistor by a second layer of insulating material.
The act of charging the floating gate is termed the "program" step for a flash EPROM. This is accomplished through a so-called hot-electron injection by establishing a large positive voltage between the gate and source, as much as 12 volts, and a positive voltage between the drain and source, for instance, 7 volts.
The act of discharging the floating gate is called the "erase" function for a flash EPROM. This erasure function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase). For instance, a source erase operation is induced by establishing a large positive voltage from the source to gate, while floating the drain of the respective memory cell. This positive voltage may be as much as 12 volts.
FIG. 1 depicts flash memory cell 10, which is an EPROM with tunnel oxide. Memory cell 10 is formed on a p-substrate 60. Source 57 and drain 55 are formed in substrate 60. Floating gate 53 separates control gate 50 from drain 55 and source 59.
In order to programmemory cell 10, the threshold voltage of the cell is raised by means of channel-hot electron injection. Control gate 50 and drain 55 are connected to a high voltage, and source 59 is connected to ground. The Vg voltage applied to gate 50 is greater than the Vd voltage applied to drain 55. Electrons 52 are forced into floating gate 53 by means of channel-hot electron injection. The electrons charge the floating gate of cell 10. The threshold voltage is changed to a high threshold state, and cell 10 is in a programmed state. In this programmed state, when a read voltage is applied to cell 10, the read voltage is not high enough to cause memory cell 10 to turn on or conduct.
FIG. 2, is a plot of a threshold voltage distribution of programmed and erased memory cells. The X-axis represents the number of memory cells and the Y-axis corresponds to the threshold voltage of memory cells. Inherent variations in the tolerance and processing of the memory cells cause the threshold voltage of the memory cells to be distributed. Referring to FIG. 2, the threshold voltage of cells in the programmed state is greater than 6.5 volts and the threshold voltage of cells in the erased state is limited from 0.5 volts to 3.5 volts.
Erasing of the memory cell by source erase is accomplished by moving the electrons from the floating gate to the source. Removing the electrons from the floating gate lowers the threshold voltage of the memory cell and cause the memory cell to turn on or conduct when the read voltage is applied.
FIG. 3 depicts memory cell 10 as it is erased from a programmed state. Erasing is preformed by Fowler-Nordheim tunneling of the electrons from the floating gate to the source diffusion layer by grounding control gate 50 and applying a high voltage to source 57. The Vpp voltage applied to source 57 can be as much as 12 volts. Electrons 52 are moved from floating gate 53 to source 57.
Erasing of the memory cells can be done by repeated applications of the Vpp voltage to the source. After each application of the Vpp voltage, which can last about 100 msec, a read voltage is applied to the memory cells and the draw current of the memory cells are measured. The draw current is measured to verify that the memory cells are properly erased. If the measured draw current is lower than expected, there are memory cells that are not completely erased. Memory cells that are programmed will not draw current during the read mode, thus, by measuring the draw current it is possible to verify whether the memory cells are properly erased. Repeated pulses of the Vpp voltage is applied to the source until the measured draw current is within the specified limits to indicate the proper erasure of the memory cells.
The number of repeated applications of the Vpp voltage varies between cells because variations in the tolerance and processing cause different behaviors between memory cells. Other factors also affect the behavior of memory cells. For instance, as the number of program and erase cycles experienced by the memory cells increase, the number of Vpp applications also increases before the memory cells can be properly erased.
Excessive applications of Vpp to electrically erase the memory cells cause undesirable effects to memory cells. One characteristic of negative gate erase is that it is not self-limiting. A phenomena known as over-erasing occurs when too many electrons are removed from the floating gate which leaves the floating gate positively charged. Over-erasing is caused by the repeated application of the Vpp pulse to a memory cell that has already been properly erased. Different memory cells require a different number of Vpp applications to be properly erased. Memory cells that require less number of Vpp applications will be over-erased because electrical erase is not self-limiting. Each application of the Vpp voltage removes electrons from the floating gate to the source. When too many electrons are removed from the floating gate by repeated applications of Vpp voltage, the memory transistor becomes a depletion-mode transistor or a transistor that is always turned on. The depletion mode transistor causes bit-line leakage current during reading of the cells and causes false readings. More importantly, the leakage current draws power away from the programming voltage which reduces the programming voltage and causes the programming of cells to fail.
There have been several solutions to the over-easing problem. A series enhancement transistor used in electrically erasable programmable read only memories (EEPROMs) can be employed to prevent the leakage current. The memory cell can be viewed as two transistors in series. One transistor is a floating-gate memory transistor, similar to memory cell 10. The other transistor is a simple enhancement transistor controlled by the control gate of the memory transistor. The series enhancement transistor is used as a select transistor to provide access to the memory cell only when the memory cell is selected. The leakage current caused by over-erasing is avoided by not permitting the over-erased transistors to contribute to the read current. The drawbacks of the enhancement transistor are the loss of space for memory cells and the added complexity of the select circuit.
A technique called verified-erase can be used to reduce the over-erase problem. An initial erase step is carried out by erasing from the source junction of all cells in the memory array. The erase voltage is applied to the sources with all control gates grounded. Subsequently, a read operation is performed with a voltage of approximately 3.2 volts applied to the control gate. The voltage applied is the upper limit for the threshold voltage of a cell in the erase state. The current for the memory cells is measured to determine whether the memory cells have been erased. If some bits require more time to reach the erase state, erasing is performed again. The erase verify sequence is repeated until all cells in the array have a threshold voltage of at least the upper limit for the threshold voltage of a cell in the erase state. Given that read operations are performed at 5 volts, this ensures removal of a sufficient amount of charge from the floating gate with a margin for safety over the minimum required for successful erase. The verified-erase technique does not provide a solution but avoids the problem of over-erasing.
A self-convergence erasing mechanism can be used to solve the over-erasing problem. This mechanism is described in a published paper entitled "A Self-Convergence Erasing Scheme For A Simple Stacked Gate Flash EPROM," IEEE Tech. Dig. IEDM 1991, pp 307-310. The publication was presented by S. Yamada, T. Suzuki, E. Obi, M. Oshikiri, K. Naruke, and M. Wada. The self-convergence erasing mechanism utilizes avalanche-hot carrier injection after erasure by Fowler-Nordheim tunneling. The avalanche-hot carrier injection causes the threshold voltages of the memory cells to converge to a certain "steady-state". The steady-state is reached when there is a balance between avalanche-hot electron injection and avalanche-hot hole injection of the floating gate. Using this mechanism, the threshold voltage of over-erased memory cells can be raised to a higher level.
Referring to FIG. 3a, memory cell 10 is connected to perform the self-convergence erasing mechanism. A drain voltage Vd of approximately 6 volts is applied to drain 55. Gate 50 and source 57 are grounded. The drain voltage Vd is applied until the threshold voltages of the memory cells converge to a steady-state.
FIG. 3b as disclosed in Yamada, et al. plots the threshold voltages for a flash memory cell as a function of the drain disturb time with different starting threshold voltages as parameters. The X-axis represents the drain disturbed time in milliseconds and the Y-axis represents the threshold voltage of the memory cells. The findings of Yamada, et al. show that threshold voltages that are below the UV-erased condition are effected by the drain disturb voltage. The effects of the drain disturb voltage cause the threshold voltages to converge to a steady-state threshold voltage.
FIG. 3c is also disclosed in Yamada, et al. FIG. 3c plots the characteristics of the gate current Ig as a function of the gate voltage Vg for the memory cells. The X-axis represents the gate voltage Vg, and the Y-axis represents the log of the gate current. Vg* represents the point where hole injection and electron injection are in balance. Data trace 58 shows that the avalanche-hot hole injection occurs at low bias when the gate voltage Vg is greater than 0 volts but is less than Vg*. Data trace 59 shows that channel-hot electron injection occurs at a higher gate bias. Electron injection occurs at gate voltages greater than Vg*.
In a stacked gate structure such as a floating gate, three scenarios occur depending on the value of the gate voltage Vg. The first scenario is represented by data trace 59 where the gate voltage Vg is greater than Vg*. Electrons are injected into the floating gate which decreases the gate voltage until the gate voltage equals Vg*. The second scenario is represented by data trace 58 where holes are injected into the floating gate. The injected holes increase the gate voltage until the gate voltage equals Vg*. The third scenario is where the gate voltage is less than 0 volts. Channel electron induced hot carrier injection does not occur when the gate voltage is less than 0 volts.
As shown in FIG. 3b, the effect of drain disturb upon threshold voltages that are near or above the UV-erased condition (UV-Vt) is minimal. The threshold voltages do not shift as a result of the drain disturb voltage. Only those threshold voltages lower than the UV-erased condition are effected by the drain disturb voltage and converge to a steady-state.
The self-convergence mechanism provides an intermediate solution to the problems of over-erasing. Avalanche-hot carrier injection is utilized to converge the threshold voltages to a steady-state. However, avalanche-hot hole injection of the gate is known to cause device degradation. Device degradation effects the longevity and reliability of the device. Although the self-convergence mechanism does provide a tighter threshold voltage distribution after erase, the disadvantage is that the distribution spread is limited to the difference between UV-Vt and the steady-state convergence threshold voltage. As FIG. 3b shows, the distribution between UV-Vt and the steady-state convergence threshold voltage is around 2 volts. Tightening the distribution spread is desirable because designed safety margins accounting for the distribution spread of the threshold voltages can be reduced. Speed is also a major consideration in memory devices. Any increase in speed at which devices can operate is further desirable.
Accordingly, disadvantages of the current self-convergence mechanism include device degradation affecting reliability, set threshold voltage distribution spread, and the self-convergence speed.
Therefore, it is desirable to design a circuit to provide a tight voltage threshold distribution that improves and overcomes the disadvantages of the prior art.